Source Synchronous Interfaces (SSIs) are parallel chip-to-chip interfaces with a forwarded clock. In a SSI, the transmitting side (commonly referred to as TX) sends clock together with data, and the receiving side (commonly referred to as RX) latches the incoming data with the incoming clock. For example, FIG. 1 shows a typical TX (output) implementation of a double-data-rate (DDR) SSI, and FIG. 2 shows a typical RX (input) implementation of a DDR SSI.
SSIs eliminate chip-to-chip interface speed limitations due to clock skew and data propagation delays between chips, thereby significantly boosting the speed range of parallel interfaces. SSIs offer high total throughput at relatively low per-pin data rate and low implementation cost compared to high-speed transceivers. Because of the attractive performance and cost factors, mid to high-speed chip-to-chip interfaces in current VLSI-based systems are commonly implemented as source synchronous, very often as DDR, interfaces. Many variations of SSIs have been adopted as industry standards, such as XGMII (10 Gigabit Medium Independent Interface), RGMII (Reduced Gigabit Medium Independent Interface), SFI4 (SERDES to Framer Interface, Level 4), RapidIO, PCI-X, HyperTransport, DDR/QDR memory interfaces, and the like. Additionally, numerous variations are in use in proprietary forms.
In general, the speed of SSIs is limited by the following factors: (1) skew across the entire parallel bus, including data; (2) total jitter on data and clock channels; (3) duty cycle distortion on clock and data paths; (4) simultaneous switching output (SSO) noise; and (5) width of interface (the wider the interface, the more skew is expected).
Due to the high-speed nature and the foregoing-indicated limitations, SSIs are commonly implemented as custom-designed hard macros. The components in the interface are carefully designed to achieve minimal duty cycle distortion and maximum balance between propagation delays through different paths.
Platform-based IC (integrated circuit) design is a powerful concept for coping with the increased pressure on time-to-market, design and manufacturing costs. A platform is a large-scale, high-complexity semiconductor device that includes one or more of the following elements: (1) memory; (2) an embedded processor; (3) other IP (intellectual property) block; (4) a customizable array of transistors (the “transistor fabric”); (5) an embedded programmable logic block; and (6) interconnect. RapidChip™, developed by LSI Logic Corp. is an instance of a platform. The transistor fabric and/or the embedded programmable logic block may give the platform its key attribute of customizability (i.e., the ability for users to create unique IC products). The basic idea behind platform-based design is to avoid designing and manufacturing a chip from scratch. Some portion of the chip's architecture is predefined or diffused for a specific type of application. This portion is fixed (not customizable). Through extensive design reuse, platform-based design may provide faster time-to-market and reduce design cost.
Under a platform approach, there are two distinct steps entailed in creating a final end-user product: a prefabrication step and a customization step. In a prefabrication step, a set of slices is built on a wafer. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the metal layers or top metal layers to implement the customer's unique design. For example, the RapidChip™ Integrator family, developed by LSI Logic Corp., is a family of slices. One or more slices may be built on a single wafer. It is understood that a slice may include one or more bottom metal layers or may include no metal layers at all. In a preferred embodiment of the prefabrication step, portions of the metal layers are pre-specified to implement the pre-defined blocks of the platform and the diffusion processes are carried out in a wafer fab. That is, the base characteristics, in terms of the IP, the processors, the memory, the programmable logic and the customizable transistor array, are all pre-placed in the design and pre-diffused in the slice. Thus, a slice is essentially a partially manufactured IC. The customer must introduce its unique functionality into the slice, making it a complete device. The customer-designed function is implemented by defining the interconnection of the elements of the transistor fabric to reflect the desired functionality. This interconnection is mapped into a set of metal layers, merged with the pre-defined blocks, and the metal layers (or late-metal components) are laid down, completing the device. Thus, the transistor fabric may be used to create the unique aspects of the design. The remaining (non-customizable) regions of the slice may be referred to as diffused logic.
In a conventional approach, because each SSI needs to be custom designed with special components, the interface hard macro often need be diffused in the slice of a platform. However, each diffused hard macro takes away otherwise usable die area and occupies valuable chip IOs. Moreover, a diffused hard macro supports only a fixed interface. Due to the numerous variations of SSIs, the flexibility of a slice with a particular diffused interface is limited. Consequently, a large number of slices may be required to support the different variations, making the support of SSIs in a platform very costly. Thus, the conventional approach of dedicated, custom designed hard macros for implementing SSIs presents serious challenges to the value proposition of the platform-based IC design.
As indicated above, the conventional approach relies on building dedicated, custom designed hard macros for implementing SSIs. Those of ordinary skill in the art will understand that only for low speed applications may the interface hard macros be built directly with the native transistor fabric embedded in a slice. For nearly all mid to high-speed applications, at least some diffused circuitry is required. For the 0.13-micron process node, the “mid-speed” frequency range is roughly 250 to 1000 MHz.
Thus, it would be desirable to provide a method and apparatus for implementing various types of SSIs for a platform based on a common SSI architecture.